Following energizing or re-energizing of an integrated circuit (IC), such as a memory device, microcontroller or processor, system-on-chip (SoC) or programmable SoC (PSoC), trim information for operating references, regulators, clocks, etcetera, is copied from a non-volatile memory to volatile latches or trim registers in a main circuit of the IC. The majority of trim information is copied in software to relevant trim registers as part of a boot process. A small portion of the trim information, however, is required to be valid prior to the boot process to ensure that the IC has usable power supplies, reference and regulator voltages, clocks, and the correct state(s) on certain input/output pins before the IC transitions out of its power-on reset state and begins the boot process. This initial trim information is programmed only once during manufacturing.
One problem with conventional circuits and methods for setting initial trim bits in the IC is that differences between the non-volatile memory and main circuit of the IC, such as variations in process, voltage, and temperature (PVT) corners of devices, can result in recalling or transferring trim bits to the trim registers in the IC before a power supply voltage (VDD) has risen sufficiently high to ensure the trim bits are valid. Prior approaches to addressing this problem have used a separate power supply supervisor circuit, which asserts a power good signal to trigger transferring of trim bits after VDD is above a pre-determined threshold. This approach has not been wholly satisfactory as the addition of a separate power supply supervisor circuit adds to the cost, complexity, standby current, and size of the IC. Moreover, the approach has not been entirely effective because of interdependencies resulting from uncorrelated PVT variations in the non-volatile memory, trim registers and power supply supervisor circuit result in difficult design challenges, which often require multiple rework cycles to ensure proper operation.